设计了一款低功耗12bit 100MS/s流水线逐次逼近型模数转换器(Pipelined SAR ADC),提出了一种第二级子模数转换器时间交织的结构,改善了模数转换器的采样率;优化Pipelined SAR ADC前后级子ADC的位数关系,同时结合半增益运算放大器技术,降低了运放的设计难度,减小了运放的功耗.本设计是在TSMC65nm LP工艺下设计实现的,在电源电压为1.2V,采样率为100MS/s,输入信号为49.1MHz时,此ADC可达到69.44dB的信噪比(SNDR)和74.04dB的无杂散动态范围(SFDR),功耗为8.6mW.
This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and maintains 51dB up to 57MHz, the Nyquist frequency for a clock rate of 100Msample/s. The differential non-linearity （DNL） and integral non-linearity （INL） are typically measured as 0.3LSB and 1.0LSB, respectively. The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm^2.
