研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。
The degradation of MOS transistor operation due to soft breakdown of the gate oxide is studied.Important transistor parameters are monitored under homogeneous stress at different temperature until the soft breakdown occurred.The output and transfer characteristic have small change after soft breakdown as the degradations of drain current and threshold voltage is continuous.However,the increment of gate leakage current increases abruptly after the soft breakdown.The analysis to the increment of gate leakage current after the soft breakdown shows mechanism of similar Fowler Nordheim(FN) tunneling current.
Stress-induced leakage current (SILC) of ultrathin gate oxide is investigated by observing the generation of interface traps for n-MOSFET and p-MOSFET under hot-carrier stress.It is found experimentally that there is linear correlation between the generation of interface traps and SILC for both types of MOSFET with different channel lengths (including 1,0.5,0.275,and 0.135μm) and different gate oxide thickness (4nm and 2.5nm).These experimental evidences show that the SILC has a strong dependence on interface traps.
