High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.
通过对支持向量数据描述SVDD(Support Vector Data Description)算法的阐述和SVDD算法在增量学习过程中支持向量集变化特性的分析,提出一种新的SVDD增量学习算法。以Spambase邮件语料库作为实验数据源,将其与非增量学习算法以及一般传统增量学习算法进行比较,结果证明,该算法在保证垃圾邮件识别精度的同时又大大缩短了训练时间。
