An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process.The circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass band.Instead of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption.In the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 dB.The OIP3 is 23.3 dBm at the gain of 10 dB.Simulation results show that the settling time is reduced from 100 to 1 ms.The image band rejection is about 40 dB.It only draws 4.5 mA current from a 1.8 V supply voltage.
A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.
