The degradation mechanism of enhancement-mode Al Ga N/Ga N high electron mobility transistors（HEMTs） fabricated by fluorine plasma ion implantation technology is one major concern of HEMT＇s reliability. It is observed that the threshold voltage shows a significant negative shift during the typical long-term on-state gate overdrive stress. The degradation does not originate from the presence of as-grown traps in the Al Ga N barrier layer or the generated traps during fluorine ion implantation process. By comparing the relationships between the shift of threshold voltage and the cumulative injected electrons under different stress conditions, a good agreement is observed. It provides direct experimental evidence to support the impact ionization physical model, in which the degradation of E-mode HEMTs under gate overdrive stress can be explained by the ionization of fluorine ions in the Al Ga N barrier layer by electrons injected from 2DEG channel.Furthermore, our results show that there are few new traps generated in the Al Ga N barrier layer during the gate overdrive stress, and the ionized fluorine ions cannot recapture the electrons.
Negative bias temperature instability（NBTI） has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery of NBTI systemically under different conditions in the P-type metal–oxide–semiconductor field effect transistor（PMOSFET）, explain the various recovery phenomena, and find the possible processes of the recovery.
GaNs grown by hydride vapor phase epitaxy(HVPE) were irradiated by protons with different fluences.The changes of surface topography of as-grown and irradiated samples were characterized by atomic force microscopy(AFM).The crystal quality and optical properties of GaN films were examined by the variations of the micro-Raman and photoluminescence(PL) spectra with proton fluence.It was observed that the surface became a little more rough after irradiation.The Raman spectra indicated that the strain of materials and carrier concentration were not affected by the proton injection.The full-width at half-maximum(FWHM) of E 2 high phonon mode narrowed,which was consistent with the FWHM of PL near-band-edge emission(BE).The spectra of yellow luminescence and blue luminescence normalized to the intensity of BE demonstrated a little increase of Ga vacancy and a large decrease of O N,which may be the main reason for the change of optical properties.
LU LingHAO YueZHENG XueFengZHANG JinChengXU ShengRuiLIN ZhiYuAI ShanMENG FanNa
Frequency-dependent conductance measurements were carried out to investigate the trap states induced by reactive ion etching in A1GaN/GaN high-electron-mobility transistors （HEMTs） quantitatively. For the non-recessed HEMT, the trap state density decreases from 2.48 × 1013 cm-2.eV-1 at an energy of 0.29 eV to 2.79 × 1012 cm-2.eV-1 at ET = 0.33 eV. In contrast, the trap state density of 2.38 × 1013-1.10× 1014 cm-2.eV-1 is located at ET in a range of 0.30-0.33 eV for the recessed HEMT. Thus, lots of trap states with shallow energy levels are induced by the gate recess etching. The induced shallow trap states can be changed into deep trap states by 350 ℃ annealing process. As a result, there are two different types of trap sates, fast and slow, in the annealed HEMT. The parameters of the annealed HEMT are ET = 0.29-0.31 eV and DT = 8.16× 1012-5.58 × 1013 cm-2.eV-1 for the fast trap states, and ET = 0.37-0.45 eV and DT = 1.84×1013- 8.50 × 1013 cm-2.eV-1 for the slow trap states. The gate leakage currents are changed by the etching and following annealing process, and this change can be explained by the analysis of the trap states.
Low-density drain high-electron mobility transistors（LDD-HEMTs） with different F plasma treatment were investigated by simulations and experiments.The LDD region was performed by introducing negatively charged fluorine ions,which modified the surface field distribution on the drain side of the HEMT,and the enhancement of breakdown voltage were achieved.With the increased fluorine plasma treatment power and LDD region length,the breakdown voltage can be maximumly improved by 70%,and no severe reductions on output current and transconductance were observed.To confirm the temperature stability of the devices,annealing experiments were carried out at 400 ℃ for 2 min in ambient N_2.Moreover,the gate leakage current and breakdown voltage before and after annealing were compared and analyzed,respectively.
In this paper, we present the combination of drain field plate （FP） and Schottky drain to improve the reverse blocking capability, and investigate the reverse blocking enhancement of drain FP in Schottky-drain AlGaN/GaN high-electron mobility transistors （HEMTs）. Drain FP and gate FP were employed in a two-dimensional simulation to improve the reverse blocking voltage （VRB） and the forward blocking voltage （VFB）. The drain-FP length, the gate-FP length and the passivation layer thickness were optimized. VRB and VFB were improved from -67 V and 134 V to -653 V and 868 V respectively after optimization. Simulation results suggest that the combination of drain FP and Schottky drain can enhance the reverse blocking capability significantly.
The effect of the static negative bias temperature （NBT） stress on a p-channel power metal-oxide-semiconductor field-effect transistor （MOSFET） is investigated by experiment and simulation. The time evolution of the negative bias temperature instability （NBTI） degradation has the trend predicted by the reaction-diffusion （R-D） model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R-D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.
In this paper, the principle of discharge-based pulsed I–V technique is introduced. By using it, the energy and spatial distributions of electron traps within the 4-nm HfO_2 layer have been extracted. Two peaks are observed, which are located at ？E ^-1.0 eV and-1.43 eV, respectively. It is found that the former one is close to the SiO_2/HfO_2 interface and the latter one is close to the gate electrode. It is also observed that the maximum discharge time has little effect on the energy distribution. Finally, the impact of electrical stress on the HfO_2 layer is also studied. During stress, no new electron traps and interface states are generated. Meanwhile, the electrical stress also has no impact on the energy and spatial distribution of as-grown traps. The results provide valuable information for theoretical modeling establishment, material assessment,and reliability improvement for advanced semiconductor devices.
