In this paper, 0.15-μm gate-length In0.52Al0.48As/In0.53Ga0.47As InP-based high electron mobility transistors （HEMTs） each with a gate-width of 2×50 μm are designed and fabricated. Their excellent DC and RF characterizations are demonstrated. Their full channel currents and extrinsic maximum transconductance （gm,max） values are measured to be 681 mA/mm and 952 mS/mm, respectively. The off-state gate-to-drain breakdown voltage （BVGD） defined at a gate current of-1 mA/mm is 2.85 V. Additionally, a current-gain cut-off frequency （fT） of 164 GHz and a maximum oscillation frequency （fmax） of 390 GHz are successfully obtained; moreover, the fmax of our device is one of the highest values in the reported 0.15-μm gate-length lattice-matched InP-based HEMTs operating in a millimeter wave frequency range. The high gm,max, BVGD, fmax, and channel current collectively make this device a good candidate for high frequency power applications.
Design and fabrication of a Ka-band voltage-controlled oscillator（VCO） using commercially available 1-μm GaAs heterojunction bipolar transistor technology is presented.A fully differential common-emitter configuration with a symmetric capacitance with a symmetric inductance tank structure is employed to reduce the phase noise of the VCO,and a novel π-feedback network is applied to compensate for the 180° phase shift.The on-wafer test shows that the VCO exhibits a phase noise of-96.47 dBc/Hz at a 1 MHz offset and presents a tuning range from 28.312 to 28.695 GHz.The overall dc current consumption of the VCO is 18 mA with a supply voltage of-6 V.The chip area of the VCO is 0.7×0.7 mm^2.
AHfO2/n–In Al As MOS-capacitor has the advantage of reducing the serious gate leakage current when it is adopted in In As/Al Sb HEMT instead of the conventional Schottky-gate. In this paper, three kinds of Hf O2/n–InAlAs MOS-capacitor samples with different Hf O2 thickness values of 6, 8, and 10 nm are fabricated and used to investigate the interfacial and electrical characteristics. As the thickness is increased, the equivalent dielectric constant ε ox of Hf O2 layer is enhanced and the In AlAsHfO2 interface trap density Ditis reduced, leading to an effective reduction of the leakage current. It is found that the Hf O2 thickness of 10 nm is a suitable value to satisfy the demands of most applications of a HfO2/n–InAlAs MOS-capacitor, with a sufficiently low leakage current compromised with the threshold voltage.
Al2O3and HfO2thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition(ALD).The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy(AR-XPS).It is demonstrated that the Al2O3layer can reduce interfacial oxidation and trap charge formation.The gate leakage current densities are 1.37×106A/cm2and 3.22×106A/cm2at+1V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively.Compared with the HfO2/InAlAs metal-oxide-semiconductor(MOS) capacitor,the Al2O3/InAlAS MOS capacitor exhibits good electrical properties in reducing gate leakage current,narrowing down the hysteresis loop,shrinking stretch-out of the C-V characteristics,and significantly reducing the oxide trapped charge(Qot) value and the interface state density(Dit).
The design and measured results of a broad-band direct quadrature phase shift keying(QPSK) modulator and demodulator are described in this paper.The circuits are fabricated using 1-m GaAs HBT technology.To suppress the local oscillator(LO) leakage,the double-balanced mixer is selected as the core unit in the modulator/demodulator.An embedded four-way quadrature divider which includes a Lange coupler and two Baluns is utilized in the system to generate quadrature-phase LO signals.As results of a back-to-back test,the system can operate at data rates in excess of 2 Gb/s(1 Gb/s per I and Q channels) at 30 GHz.The supplies of the modulator and demodulator are 5.0 V and 4.5 V with size of 1.35 mm×3.5 mm and 1.36 mm×3.4 mm,respectively.
We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
The design and test results of a 6-bit 3-Gsps analog-to-digital converter （ADC） using 1 μm GaAs het- erojunction bipolar transistor （HBT） technology are presented. The monolithic folding-interpolating ADC makes use of a track-and-hold amplifier （THA） with a highly linear input buffer to maintain a highly effective number of bits （ENOB）. The ADC occupies an area of 4.32 × 3.66 mm2 and achieves 5.53 ENOB with an effective resolution bandwidth of 1.l GHz at a sampling rate of 3 Gsps. The maximum DNL and INL are 0.36 LSB and 0.48 LSB, respectively.
This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.
