A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.
An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor(UMOSFET) integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.
An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor（UMOSFET） integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.
