The GaAs MOS capacitor was fabricated with HfTiON as high-k gate dielectric and NH3-plasma-treated ZnON as interfacial passivation layer （IPL）, and its interracial and electrical properties are investigated compared to its counterparts with ZnON IPL but no NH3-plasma treatment and without ZnON IPL and no plasma treatment. Experimental results show that low interface-state density near midgap （1.17×10^12 cm^-2eV^-1） and small gate leakage current density have been achieved for the GaAs MOS device with the stacked gate dielectric of Hf-TiON/ZnON plus NH3-plasma treatment. These improvements could be ascribed to the fact that the ZnON IPL can effectively block in-diffusion of oxygen atoms and out-diffusion of Ga and As atoms, and the NH3-plasma treatment can provide not only N atoms but also H atoms and NH radicals, which is greatly beneficial to removal of defective Ga/As oxides and As-As band, giving a high-quality ZnON/GaAs interface.
The effects of different NH3-plasma treatment procedures on interracial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HtTiON/TaON were investigated. The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer （TaON） deposition, or after deposition ofhigh-k dielectric （HfriON）. It was found that the excellent interface quality with an interface-state density of 4.79 × 101l eV-lcm-2 and low gate leakage current （3.43 ×10-5 A/cm2 at Vg = 1 V） could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeOxNy, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeOx interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma.
Xiaoyu LiuJingping XuLu LiuZhixiang ChengYong HuangJingkang Gong
Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.
High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.
LaON,LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La_2O_3 using the sputtering method to fabricate Ge MOS capacitors,and the electrical properties of the devices are carefully examined.LaON/Ge capacitors exhibit the best interface quality,gate leakage property and device reliability,but a smaller k value（14.9）.LaTiO/Ge capacitors exhibit a higher k value（22.7）,but a deteriorated interface quality,gate leakage property and device reliability.LaTiON/Ge capacitors exhibit the highest k value（24.6）,and a relatively better interface quality（3.1×10^（11） eV^（-1）cm^（-2））,gate leakage property（3.6 × 10^（-3） A/cm^2 at V_g = 1V＋V_（fb）） and device reliability.Therefore,LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.
The influences of the main structure and physical parameters of the dual-gate GeOl MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium （Ge） channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect （SCE） and drain-induced barrier lowering （DIBL） effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10-18 nm and （5-9）×1017 cm-3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8-1 nm and 15-30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved： on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV.
The impact of quantum confinement on the electrical characteristics of ultrathin-channel GeO1 n- MOSFETs is investigated on the basis of the density-gradient model in TCAD software. The effects of the channel thickness （Tch） and back-gate bias （Vbg） on the electrical characteristics of GeOI MOSFETs are examined, and the simulated results are compared with those using the conventional semi-classical model. It is shown that when T^h 〉 8 rim, the electron conduction path of the GeOI MOSFET is closer to the front-gate interface under the QC model than under the CL model, and vice versa when Tch 〈 8 rim. Thus the electrically controlled ability of the front gate of the devices is influenced by the quantum effect. In addition, the quantum-mechanical mechanism will enhance the drain-induced barrier lowering effect, increase the threshold voltage and decrease the on-state current; for a short channel length （≤ 30 nm）, when Tch 〉 8 nm （or 〈 8 nm）, the quantum-mechanical mechanism mainly impacts the subthreshold slope （or the threshold voltage）. Due to the quantum-size effect, the off-state current can be suppressed as the channel thickness decreases.
An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C-V curve of MOS capacitors measured for a frequency range from 1 kHz to1 MHz.The proposed model is based on the Fermi-Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal.The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data.Simulations indicate thatthe capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface,with negligible effects from the traps far from the interface,and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed.In addition,by excluding the negligible effect of oxide-trap conductance,the model avoids the use of imaginary numbers and complex calculations,and thus is simple and intuitive.
GaAs metal–oxide–semiconductor（MOS） capacitors with HfTiO as the gate dielectric and Al2O3 or ZnO as the interface passivation layer（IPL） are fabricated. X-ray photoelectron spectroscopy reveals that the Al2O3 IPL is more effective in suppressing the formation of native oxides and As diffusion than the ZnO IPL. Consequently, experimental results show that the device with Al2O3 IPL exhibits better interfacial and electrical properties than the device with ZnO IPL： lower interface-state density（7.2×10^12 eV1cm^2/, lower leakage current density（3.60×10^7A/cm^2 at Vg D1 V） and good C–V behavior.
